1. Field of the Invention
This invention relates to power distribution system design, and in particular to managing disturbances otherwise caused by time varying current demands in an integrated circuit.
2. Description of the Related Art
Microprocessors will soon reach operating frequencies of 500 MHz and 1 GHz is expected by the turn of the century. In such microprocessors, power dissipation will be more than 40 Watts with power supply voltage levels well below 2 Volts. With the microprocessor circuits demanding peak currents in excess of 100 Amps, providing a well-regulated power (better than 10%) is a difficult challenge requiring careful optimization of chip, package, card and system.
With an average power dissipation on the order of 40 Watts, at a power supply voltage of 2 Volts, the average (i.e., RMS) current drawn by a microprocessor operating at full speed can exceed 20 Amps. Within each cycle, the peak current can be at least two times the average current. We can, therefore, expect peak currents of 40 to 50 Amps with a major high-frequency component at the nominal operating frequency (e.g., 500 MHz-1 GHz). However, as the microprocessor cycles through subroutines, enters or leaves stop-clock conditions, or even exhibits linear instruction sequence dependent variations in current demands, current surges can have additional frequency components up to the nominal operating frequency and including higher order harmonics. A well designed power distribution system should provide a well-regulated supply over the complete frequency range from the full clock speed, down through mid-frequencies, to very low frequencies characterized by sleep modes.
A variety of techniques are available to improve the AC impedance characteristics of a power distribution system. These techniques include optimal placement of decoupling structures/devices, chip layout with respect to power distribution, Controlled Collapse Chip Connection (C4) and Ball Grid Array (BGA) ball allocations associated with the supply voltages (V.sub.DD and V.sub.SS), BGA package design and layers, card layout and discretes placed on the card, connector suitability and V.sub.DD /V.sub.SS allocations, and lastly the motherboard layout, regulator choice and associated discrete components.
Unfortunately, despite conventional techniques, the trend toward lower voltages, higher currents, and higher operating frequencies creates both a greater susceptibility to power supply voltage collapse and undershoot and greater likelihood of same. Even after exploiting impedance tuning techniques, the AC impedance of a power distribution system is likely to exhibit mid-frequency resonances. Such resonances, when excited by sub-nominal operating frequency variations in current demands, can result in substantial excursions in on-chip power supply voltage which can adversely affect integrated circuit operation.
Large variations in current demands likely to excite such mid-frequency resonances can be caused by transitions between a nominal operating frequency and sleep (or stop clock) operating frequencies. In addition, such variations in current demands can be caused as the microprocessor cycles through instruction sequences. Even temporal variations in the set of execution units, busses, and corresponding circuits drawing current may excite mid-frequency components in overall current demand, which can result in excursions in on-chip power supply voltage. Data sequence dependent variations in current demands have similar effects.